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Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
CDK1303
8-bit, 1 GSPS, Flash A/D Converter
CDK1303 8-bit, 1 GSPS, Flash A/D Converter
features
n n n n n
General Description
The CDK1303 is a full parallel (flash) analog-to-digital converter capable of digitizing full scale (0 to -2V) inputs into eight-bit digital words at an update rate of 1 GSPS. The ECL-compatible outputs are demultiplexed into two separate output banks, each with differential data ready outputs to ease the task of data capture. The CDK1303's wide input bandwidth and low capacitance eliminate the need for external track-and-hold amplifiers for most applications. A proprietary decoding scheme reduces metastable errors to the 1 LSB level. The CDK1303 operates from a single -5.2V supply, with a nominal power dissipation of 5.5W. The CDK1303 is available in an 80-lead surface-mount MQUAD package over the industrial temperature range (-25C to +85C).
1:2 Demuxed ECL compatible outputs Wide input bandwidth - 900MHz Low input capacitance - 15pF Metastable errors reduced to 1 LSB Gray code output
applications
n n n n
Digital oscilloscopes Transient capture Radar, EW, and ECM Direct RF down-conversion
Block Diagram
REV 1A
Ordering Information
Part Number CDK1303AEMQ80 CDK1303AEMQ80_Q CDK1303BEMQ80 CDK1303BEMQ80_Q Package MQUAD-80 MQUAD-80 MQUAD-80 MQUAD-80 Pb-Free Yes No Yes No RoHS Compliant Yes No Yes No Operating Temperature Range -25C to +85C -25C to +85C -25C to +85C -25C to +85C Packaging Method Rail Rail Rail Rail
Moisture sensitivity level for all parts is MSL-1. (c)2008 CADEKA Microcircuits LLC www.cadeka.com
Data Sheet
Pin Configuration MQUAD-80
CDK1303 8-bit, 1 GSPS, Flash A/D Converter
CDK1303
Pin Assignments
Pin Name VEE AGND VRTF VRTS VRM VRBF VRBS VIN DGND D0-D7A D0-D7B DRA DRA DRB DRB D8A D8B CLK CLK Description Negative Supply Nominally -5.2V Analog Ground Reference Voltage Force Top, Nominally 0V Reference Voltage Sense Top Reference Voltage Middle, Nominally -1V Reference Voltage Force Bottom, Nominally -2V Reference Voltage Sense Bottom Analog Input Voltage, Can Be Either Voltage or Sense Digital Ground Data Output Bank A Data Output Bank B Data Ready Bank A Not Data Ready Bank A Data Ready Bank B Not Data Ready Bank B Overrange Output Bank A Overrange Output Bank B Clock Input Clock Input
REV 1A
(c)2008 CADEKA Microcircuits LLC
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2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
CDK1303 8-bit, 1 GSPS, Flash A/D Converter
Parameter Supply Voltages Negative Supply Voltage (VEE to GND) Ground Voltage Differential Input Voltages Analog Input Reference Input Digital Input Reference Current Input (VRT to VRB) Output Voltages Digital Output Current
Min -7.0 -0.5 +0.5 +0.5 +0.5
Max +0.5 +0.5 VEE +0.5 VEE +0.5 VEE +0.5 35 -28
Unit V V V V V mA mA
0
Reliability Information
Parameter Storage Temperature Range Min -65 Typ Max +150 Unit C
Recommended Operating Conditions
Parameter Operating Temperature Range - ambient Operating Temperature - case Operating Temperature - junction Lead Temperature, (soldering 10 seconds) Min -25 Typ Max +85 +125 +150 +300 Unit C C C C
REV 1A
(c)2008 CADEKA Microcircuits LLC
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3
Data Sheet
Electrical Characteristics
(TJ = TC = TA = +25C , VEE = -5.2V, VRB = -2.0V, VRM = -1.0V, VRT = 0.00V, CLK = 1GHz, Duty Cycle=50%, unless otherwise specified)
cDK1303a symbol parameter
Resolution
cDK1303B Max Min typ
8 +0.95 +1.0 -0.95 -1.5 +1.5 +1.5 Guaranteed VRT VRB 0.75 15 15 900 500 +30 +30 -30 -30 5 2 60 80 30 1 +30 +30 VRT 2.0 V mA k pF MHz MHz mV mV V/ns A MHz GHz 2 250 1.9 2.25 0.9 1.25 43 41 -42 -34 43 35 40 33 1.4 1.75 1.9 2.25 ps ps ns ns dB dB dBc dBc dB dB dB dB
conditions
Min
typ
8
Max
units
CDK1303 8-bit, 1 GSPS, Flash A/D Converter
bits LSB LSB
DC Performance
DLE ILE Differential Linearity Error(1) Integral Linearity Error(1) No Missing Codes clk = 100MHz clk = 100MHz -0.85 -1.0 Guaranteed VRB VIN = 0V Over Full Input Range Small Signal Large Signal VRT VRB -30 -30 5 2 60 80 30 1 2 250 0.9 1.25 IN = 50MHz(1) IN = 250MHz
(1)
Analog Input
Input Voltage Range(1) Input Bias Current(1) Input Resistance Input Capacitance Input Bandwidth Offset Error
(2)
0.75 15 15 900 500
2.0
Offset Error(2) Input Slew Rate Clock Synchronous Input Currents
Reference Input
Ladder Resistance(1) Reference Bandwidth
Timing Characteristics
Maximum Sample Rate(1) Aperture Jitter Acquisition Time CLK to Data Delay(2) CLK to Data Ready Delay(2)
REV 1A
1.4 1.75
Dynamic Performance
SNR THD SFDR SINAD
notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data. 3. Typical Thermal Impedance: JC = +4C/W.
Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range Signal-to-Noise and Distortion
45 43 -44 -36 47 39 42 35
IN = 50MHz(1) IN = 250MHz(1) IN = 50MHz
(1)
IN = 250MHz(1) IN = 50MHz(1) IN = 250MHz
(1)
(c)2008 CADEKA Microcircuits LLC
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4
Data Sheet
Electrical Characteristics
(TJ = TC = TA = +25C , VEE = -5.2V, VRB = -2.0V, VRM = -1.0V, VRT = 0.00V, CLK = 1GHz, Duty Cycle=50%, unless otherwise specified)
cDK1303a symbol parameter
Input High Voltage(1) Input Low Voltage tPWH tPWL
(1)
cDK1303B Max Min
-1.1 -1.5 0.5 0.5 -1.1 -1.5
conditions
CLK, CLK CLK, CLK
Min
-1.1 0.5 0.5 -1.1
typ
-0.7 -1.8 0.4 0.4 -0.9 -1.8 450 450
typ
-0.7 -1.8 0.4 0.4 -0.9 -1.8 450 450
Max
units
CDK1303 8-bit, 1 GSPS, Flash A/D Converter
Dynamic Inputs
V -1.5 V ns ns V -1.5 V ps ps -5.45 1.2 6.25 V A W
Clock Pulse Width High(1) Clock Pulse Width Low(1) Logic 1 Voltage(1) Logic 0 Voltage(1) Rise Time Fall Time 20% to 80% 20% to 80%
Digital Outputs
Power Supply Requirements
VEE IEE Voltage Range(2) Current
(1)
-4.95 VIN = 0V
-5.2 1.05 5.5
-5.45 1.2 6.25
-4.95
-5.2 1.05 5.5
Power Dissipation(1)
notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data. 3. Typical Thermal Impedance: JC = +4C/W.
REV 1A
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
General Description
The CDK1303 is one of the fastest monolithic 8-bit parallel flash A/D converters available today. The nominal conversion rate is 1 GSPS and the analog bandwidth is in excess of 900MHz. A major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators (see block diagram). This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta, but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so that it remains constant over different input voltage and frequency ranges and
therefore makes the part easier to drive than previous flash converters. The preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to "trip" into or out of the active state. This gain reduces metastable states that can cause errors at the output. The CDK1303 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The output drive capability of the device can provide full ECL swings into 50 loads.
CDK1303 8-bit, 1 GSPS, Flash A/D Converter
REV 1A
Figure 1. Typical Interface Circuit Diagram
(c)2008 CADEKA Microcircuits LLC
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6
Data Sheet
Typical Interface Circuit
The circuit in Figure 1 is intended to show the most elaborate method of achieving the least error by correcting for integral linearity, input induced distortion, and power supply/ ground noise. This is achieved by the use of external reference ladder tap connections, input buffer, and supply decoupling. Please contact the factory for the CDK1303 evaluation board application note that contains more details on interfacing the CDK1303. The function of each pin and external connections to other components is as follows: VEE, AGND, DGND VEE is the supply pin with AGND as ground for the device. The power supply pins should be bypassed as close to the device as possible with at least a 0.01F ceramic capacitor. A 10F tantalum can also be used for low frequency suppression. DGND is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in Figure 1. VIN (Analog Input) There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The CDK1303 is superior to similar devices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has constant capacitance and induces less slew rate distortion. CLK, CLK (Clock Inputs) The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. D0 To D8, DR, DR, (A and B) The digital outputs can drive 50 to ECL levels when pulled down to -2V. When pulled down to -5.2V, the outputs can drive 130 to 1k loads. All digital outputs are grey code with the coding as shown in Table 1. Cadeka recommends using differential receivers on the outputs of the data ready lines to ensure the proper output rise and fall times.
VRBF, VRBS, VRTF, VRTS, VRM (Reference Inputs) There are two reference inputs and one external reference voltage tap. These are -2V (VRB force and sense), midtap (VRM) and AGND (VRT force and sense). The reference pins and tap can be driven by op amps as shown in Figure 1 or VRM may be bypassed for limited temperature operation. These voltage inputs can be bypassed to AGND for further noise suppression if so desired. Table 1. Output Coding
Vin > -0.5 LSB -0.5 LSB -1.5 LSB * * * > -1.0V * * * -2.0V +0.5 LSB < (-2.0V +0.5 LSB) D8 1 1 0 0 0 * * * 0 0 * * * 0 0 0 D7-D0 10000000 10000000 10000000 10000000 10000001 * * * 11000000 01000000 * * * 00000001 00000000 00000000
CDK1303 8-bit, 1 GSPS, Flash A/D Converter
REV 1A
Indicates the transition between the two codes
Thermal Management
The typical thermal impedance is as follows: CA = +17 C/W in still air with no heat sink We highly recommend that a heat sink be used for this device with adequate air flow to ensure rated performance of the device. We have found that a Thermalloy 17846 heat sink with a minimum air flow of 1 meter/second (200 linear feet per minute) provides adequate thermal performance under laboratory tests. Application specific conditions should be taken into account to ensure that the device is properly heat sinked.
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Operation
The CDK1303 has 256 preamp/comparator pairs which are each supplied with the voltage from VRT to VRB divided equally by the resistive ladder as shown in the block diagram. This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input voltage applied at VIN is connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each one's individual clock buffer. When the CLK pin is in the low state, the master or input stage of the comparators compare the analog input voltage to the respective reference voltage. When the CLK pin changes from low to high the comparators are latched
to the state prior to the clock transition and output logic codes in sequence from the top comparators, closest to VRT (0V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when the CLK is changed from high to low. At the output of the decoders is a set of four 7-bit latches which are enabled ("track") when the clock changes from high to low. From here, the output of the latches are coded into 6 LSBs from 4 columns and 4 columns are coded into 2 MSBs. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs.
CDK1303 8-bit, 1 GSPS, Flash A/D Converter
N VIN
N+1 1.0 ns N+2 N+3 N+4
N+5
N+6 N+7
CLK
CLK DRA DRA Data Bank A DRB
1.4 ns typ
REV 1A
N-2
1.75 ns typ
N
N+2
N+4
DRB Data Bank B
1.4 ns typ
N-1
1.75 ns typ
N+1
N+3
Figure 2. Timing Diagram
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
Schematic Diagrams
Input Circuit Output Circuit Clock Circuit
CDK1303 8-bit, 1 GSPS, Flash A/D Converter
Mechanical Dimensions
MQUAD-80 Package
MQUAD-80
SYMBOL A B C D E F G H I J K L M INCHES MIN TYP MAX 0.904 0.923 0.777 0.781 0.472 0.541 0.545 0.667 0.687 0.031 0.012 0.018 0.109 0.134 0.010 0.024 0.724 0.099 0.110 0 7 0.029 0.041 MILLIMETERS MIN TYP MAX 22.95 23.45 19.74 19.84 12.00 13.74 13.84 16.95 17.45 0.80 0.30 0.45 2.76 3.40 0.25 0.60 18.40 2.51 0 7 0.73 1.03
REV 1A
For additional information regarding our products, please visit CADEKA at: cadeka.com
caDeKa Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2008 by CADEKA Microcircuits LLC. All rights reserved.
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